1. Field of the Invention
The present invention relates to communication devices, and especially to communication devices for performing flow control with an opposing communication device.
2. Description of Related Art
In order to ensure interconnectivity between communication devices which are manufactured by different manufacturers, there is SPI-4 Phase 2 standard as a communication interface standard defined by OIF (Optical Internetworking Forum). The details of the SPI-4 Phase 2 standard are specified in “System Packet Interface Level 4 (SPI-4)” 15 Oct. 2003. Hereinafter, communication interface specified by the SPI-4 Phase 2 standard is referred to as SPI-4 interface.
The SPI-4 interface is an interface specified in order to interconnect a link layer device and a PHY device (see for example U.S. Pat. No. 6,522,271). A block diagram of a link layer device and a PHY device connected by the SPI-4 interface is shown in FIG. 8. The inventor has prepared FIG. 8 to explain the SPI-4 interface. A link layer device 7 shown in FIG. 8 includes a transmit unit 71 for transmitting payload data to an opposing PHY device 8 and a receive unit 72 for receiving payload data transmitted from the PHY device 8. Note that the SPI-4 Phase 2 standard defines the direction in which payload data proceeds from the link layer device 7 to the PHY device 8 as “transmit direction” and the direction in which payload data proceeds from the PHY device 8 to the link layer device 7 as “receive direction”.
As shown in FIG. 8, the SPI-4 interface includes a transmit data channel (TDAT), a transmit control channel (TCTL) and a transmit data clock channel (TDCLK). TDAT is a channel having 16 bits wide for transmitting payload data from the transmit unit 71 to the PHY device 8. TCTL is a channel for transmitting a transmit control signal from the transmit unit 71 to the PHY device 8. The transmit control signal is a signal for notifying the type of the data transmitted over TDAT to the PHY device 8. To be more specific, when TCTL is High level, it means that a control word is present on TDAT. On the other hand, when TCTL is Low level, it means that payload data is present on TDAT. TDCLK is a channel for transferring a transmit clock of TDAT and TCTL. Each signal channel of TDAT and TCTL changes its value in synchronization with both rising and falling edges of TDCLK.
An example of the transmission waveform of TDAT, TCTL and TDCLK is shown in FIG. 9. The inventor has prepared FIG. 9 to explain the SPI-4 interface. In FIG. 9, “D” indicates payload data and “PC” indicates a payload control word defined in the SIP-4 Phase 2 standard. An ATM cell and an IP packet, etc. which are transmitted to the PHY device 8 are mapped in the payload data section of TDAT. The details of payload data is illustrated in SPI-4 Phase 2 standard (see FIG. 5.2 for example).
Furthermore, the SPI-4 interface includes a transmit status channel (TSTAT) and a transmit status clock channel (TSCLK). TSTAT is a channel having 2 bits wide for transmitting FIFO information from the PHY device 8 to the transmit unit 71. The FIFO information transmitted over TSTAT is information indicating the usage status of a FIFO buffer which stores payload data received by the PHY device 8 over TDAT. TSCLK is a channel for transferring a transmit clock of TSTAT. Each signal channel of TSTAT changes its value is synchronization with a rising edge of TSCLK.
An example of the transmission waveform of TSTAT and TSCLK is shown in FIG. 10. The inventor has prepared FIG. 10 to explain the SPI-4 interface. In FIG. 10, “F” represents a framing pattern for indicating a start position of a data frame which is transmitted over TSTAT. The framing pattern is used for synchronizing a data frame. “S0 to S15” are status words to which FIFO information is mapped. Each of the status word indicates the amount of data stored in a FIFO buffer and expressed as 2-bit data in the SPI-4 Phase 2 standard. In the example shown in FIG. 10, as 16 status words (S0 to S15) are included in one frame of TSTAT, FIFO information concerning 16 FIFO buffers can be transferred. Moreover, “DIP2” is a parity bit for error detection. The number (length) of the status words included in one frame of TSTAT is determined according to the number of the FIFO information which should be transmitted, that is, the number of FIFO buffers. The SPI-4 Phase 2 standard refers the status words length included in one frame of TSTAT as a calendar length. Moreover, the FIFO information regarding each FIFO buffer is periodically transferred for each frame. That is, a specific time slot (status word) included in a frame of TSTAT is allocated to one of several FIFO buffers according to an identifier of each FIFO buffer and is periodically transferred for each frame.
The SPI-4 interface has the same channels as “the transmit direction” stated above also for “the receive direction” in which payload data proceeds to the link layer device 7 from the PHY device 8. Specifically, the SPI-4 interface includes a receive data channel (RDAT), a receive control channel (RCTL) and a receive data clock channel (RDCLK). Furthermore, the SPI-4 interface includes a receive status channel (RSTAT) and a receive status clock channel (RSCLK). The explanation is omitted as the usage and transmission waveform of these channels are the same as the corresponding channels in the transmit direction.
Note that the frequency of the data clocks (TDCLK and RDCLK) mentioned above is specified to be 4 times more than the frequency of the status clocks (TSCLK and RSCLK). Therefore, suppose that one period of the status clocks (TSCLK and RSCLK) is a unit time, as shown in FIG. 11, while one status word is transferred over the status channels (TSTAT and RSTAT), 8 data words can be transferred over the data channels (TDAT and RDAT). In addition, the inventor has prepared FIG. 11 to explain the difference of data transfer rate between the status channel and the data channel. Since the status channels (TSTAT and RSTAT) are 2 bits wide and the data channels (TDAT and RDAT) are 16 bits wide, the data channels has a data transfer rate of 32 times more than the data transfer rate of the status channels.
Next, components included in the link layer device 7 shown in FIG. 8 are explained. The receive unit 72 has 4 FIFO buffers 122 to 125 for storing data received over RDAT. Note that the number of FIFO buffers which should be included in the receive unit 72 is not defined by the SPI-4 Phase 2 standard and it is needless to say that the FIFO buffer number shown in FIG. 8 is an example. The data received over RDAT is stored to one of the 4 FIFO buffers 122 to 125 by a receive data distribution unit 121. A FIFO information output unit 126 generates FIFO information corresponding to storage status of the received data in the FIFO buffers 122 to 125 and outputs the generated FIFO information to RSTAT.
A data output unit 711 included in the transmit unit 71 outputs payload data and a control word to TDAT. Moreover, a FIFO information receive unit 112 outputs a stop signal to the data output unit 711 based on the FIFO information obtained from the opposing PHY device 8 through TSTAT. Note that the details of flow control using FIFO information are described later. The data output unit 711 which received the stop signal suspends outputting data to a data transmission port (not shown) connected to TDAT until the stop signal is canceled.
Subsequently, the flow control using FIFO information in the conventional SPI-4 interface is explained hereinafter. In the SPI-4 Phase 2 standard, the usage condition of the FIFO buffer for storing the data received by the data channels (TDAT and RDAT) is categorized into either of three statuses, which are STARVING, HUNGRY and SATISFIED. Furthermore, a unique bit pattern is allocated to these three usage statuses by 2-bit FIFO information. FIG. 12 shows the relationship between the usage condition of the FIFO buffer and the FIFO information. The STARVING status indicates the status in which a buffer underflow is imminent. If the amount of stored data in the FIFO buffer is less than the first threshold AE, it is judged to be the STARVING state. The bit pattern of FIFO information indicating the STARVING status is “00”. The SATISFIED status indicates that the FIFO buffer is almost full. If the amount of stored data of the FIFO buffer exceeds the second threshold AF, it is judged to be the SATISFIED status. Incidentally, it is needless to say that the second threshold AF is a larger value than the first threshold AE. The bit pattern of FIFO information indicating the SATISFIED status is “10”. Lastly, the HUNGRY state indicates the status between the STARVING status and the SATISFIED status. The bit pattern of FIFO information indicating the HUNGRY status is “01”.
The link layer device 7 and the PHY device 8 perform flow control for adjusting its own data transmission rate according to the FIFO information received from the opposing device over the status channels (TSTAT and RSTAT). Specifically, if the received FIFO information indicates the STARVING status, the highest data transmission rate is applied to the data channels (TDAT and RDAT). If the received FIFO information indicates the HUNGRY state, the data transmission rate of the data channels (TDAT and RDAT) is reduced as compared to the case of the STARVING state. Moreover, if the received FIFO information indicates the SATISFIED status, data transmission over the data channels (TDAT and RDAT) at least for a FIFO buffer which is in the SATISFIED status is suspended until the FIFO information changes.
There are two problems described below in the flow control using the FIFO information in the conventional SPI-4 interface.
The first problem is that priorities cannot be given to FIFO information. With the conventional SPI-4 interface, all the FIFO information that indicates the status of each of the plurality of FIFO buffers is uniformly transferred to the opposite side periodically over the status channels (TSTAT and RSTAT). Therefore, the conventional SPI-4 interface is difficult to deal with an urgent transmission request of FIFO information which is generated unexpectedly.
The second problem is that as the calendar length increases, a maximum value (hereinafter referred to as worst response time) of time required from a generation of a status change of the FIFO buffer until a flow control is performed by an opposing device also increases. The longer the worst response time, the lower the second threshold AF must be specified, thus the abovementioned second problem causes to reduce utilization efficiency of the FIFO buffer.
The second problem is explained in detail with reference to FIGS. 13 and 14. The inventor has prepared FIGS. 13 and 14 to explain the second problem. FIG. 13 shows an example of a data frame transferred over RSTAT. According to the example of FIG. 13, FIFO information concerning 10 FIFO buffers is periodically transferred by 10 status words (S1-S10). Moreover, FIG. 13 shows response time taken from a status change of the FIFO buffer of the identification number #5 included in the link layer device from the HUNGRY status to the SATISFIED status until data transmission to RDAT by the PHY device is suspended in response to the status change. This response time is determined by the sum of delay time Lat_a, Ts and Lat_c shown in FIG. 13. Accordingly, this response time indicates the longest time pending the FIFO information S5 (information indicating the status of the FIFO buffer of identification number #5) is updated.
In FIG. 13, delay time Lat_a is time after the status of the FIFO buffer #5 changes until FIFO information is generated and updated. Ts is the time for one cycle of the period when a framing pattern is repeated. In FIG. 13, Ts is 12×status clock period (RSCLK period). Note that RSCLK period shown in FIGS. 13 and 14 is the same value with TSCLK period. Delay time Lat_c is the time after the updated FIFO information is transmitted by the link layer device until the opposing PHY device performs flow control. Note that Lat_b shown in FIGS. 13 and 14 is the time for calendar length×RSCLK period.
Among the 3 delay time mentioned above, Lat_a and Lat_c are constant. On the other hand, the delay time Lat_b varies depending on the calendar length. Therefore, worst response time LWP in the SPI-4 interface is expressed by the sum of Lat_a, Lat_c and Ts as shown in FIG. 13. Since the data frame cycle Ts of TSTAT increases as the calendar length increases, the worst response time LWP also increases as the calendar length increases.